Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed operations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
As electronic products demand smaller semiconductor devices and higher performance, various packaging types such as ball grid array (BGA), flip chip, and wafer level chip scale package (WLCSP) are being developed and refined. Flip chip technology, using copper pillars and solder cap bumps, is a popular packaging option to deliver lead-free, fine pitch, high input/output (I/O) density, and smaller form factor. For a successful packaging solution, a reliable conductive joint structure, such as a solder joint structure, is key to providing electrical connection between the semiconductor device and additional electronic devices.
Building a conductive joint structure typically involves forming a passivation layer over the active surface and contact pads of a semiconductor die. An insulating layer, such as a polyimide layer, is formed over the active surface and contact pads. A portion of the insulating layer is removed to expose the contact pads. A plurality of bumps is formed over the exposed contact pads for electrical interconnect. An under-bump metallization (UBM) layer and intermetallic compound (IMC) layers are formed between the bumps and contact pads. An extremely-low dielectric constant (ELK) insulating layer may further be formed beneath the contact pads. The polyimide insulating layer is used as a stress relief buffer and plays an important role in the reliability of flip chip products, especially when the silicon node moves to 65 μm or below. However, the placement of a polyimide layer can be complicated due to, e.g., the difference in material properties between the polyimide layer and other semiconductor components that make up the conductive joint structure. Existing conductive joint structures include the standard structure and the polyimide over UBM (POU) structure. The standard structure involves disposing the polyimide layer as a flat, continuous layer covering the entire passivation layer. The POU structure involves forming the UBM over the contact pads, and then forming the polyimide layer over the UBM.
In many cases, excessive levels of stress imposed upon a conductive joint structure may cause failure phenomena such as UBM delamination, IMC stress, ELK cracking, and bump cracking which in turn reduces reliability and manufacturing yield. For example, the passivation layer around the contact pads is known to crack, particularly around the edge of the contact pad due to stress imposed by the bumps. The passivation layer cracking leads to defects and other reliability problems.
The standard and POU structures are limited to stress minimization at specific areas of the conductive joint structure and are insufficient for minimizing the totality of stress issues imposed on a conductive joint structure. For example, standard conductive joint structures lack sufficient means for addressing high levels of mechanical stress imposed on the bumps, particularly at the edges of the bumps near the interface with the UBM. Standard conductive joint structures further exhibit weak stress relief along the polyimide layer due to the larger continuous profile of the polyimide layer used with standard structures. POU structures, on the other hand, exhibit weak stress relief with respect to IMC layers and have increased metal-to-metal contact.